The disclosed invention relates to the field of analog to digital conversion. More specifically, the disclosed invention relates to the field of analog-to-digital converters (ADCs) that use pulse width modulation (PWM).
Analog-to-digital conversion is an electronic process in which a continuously variable (analog) signal is changed, without altering its essential content, into a multi-level discretely varying digital signal. The input to an analog-to-digital converter (ADC) consists of an analog input signal. The ADC converts this input in to a digital output that has discrete levels or states. The states are represented as a combination of one or more binary digits (bits). The number of states is usually a power of two—that is, 2, 4, 8, 16, etc. The simplest digital signals have only two states, and are called binary signals.
Digital signals are preferred over analog signals for most communication applications due to two factors. First, digital signals have a high error margin compared to analog signals. Digital signals are in the form of digital impulses that are well defined and orderly. Thus, it is easier for electronic circuits to distinguish digital signals from noise. Second, a large variety of error detection and correction schemes have been developed for digital signals, while such schemes are practically non-existent for analog signals. Thus, most state of the art communication applications convert the analog data into digital data for transmission.
Further, all modern day computers perform their processing in terms of binary digital signals. These computers are used for a variety of applications that require interaction with analog interfaces. Some examples of such applications are voice processing, video processing, digital signal processing, modems and instrumentation applications. For these applications, a computer converts an analog signal to a digital signal for processing. Use of computers for the applications described above presents a need for analog-to-digital conversion. In general, in any digital signal processing system, an ADC is required if the input signal is analog. Some examples of applications that are based on ADCs are telephone modems, xDSL modems and cellular phones. A typical telephone modem makes use of an ADC to convert the incoming audio from a twisted-pair line into digital signals in a format that can be processed by a computer.
Many ADC architectures are known today. Different ADC architectures offer different advantages in terms of the speed of conversion, resolution of conversion, cost (or complexity) of implementation, power consumption, etc. A classical ADC architecture called the Flash ADC compares the input signal to a reference voltage and decodes the result into a digital signal. The Flash ADC architecture employs the fastest analog-to-digital conversion technique. However, the implementation of a Flash ADC needs 2N comparators where N is the number of bits of resolution. Resolution of an ADC can be defined as the number of bits used to represent each sample of a digital signal corresponding to an analog signal. As a result of employing 2N comparators for N bits resolution, the number of comparators increases exponentially with an increase in resolution. Hence, the power consumption increases exponentially with an increase in resolution. Thus, Flash ADCs suffer from the drawbacks of costly circuit implementations and high power consumption. Though many improved architectures for Flash ADCs have been proposed, practical solutions are limited to about 8 bits of resolution to achieve optimum performance.
Another architecture for analog-to-digital conversion is known as Pipeline ADC. Pipeline ADCs are implemented using multiple stages cascaded together. Each stage is implemented using a 2-step Flash ADC. Pipeline ADCs are cheaper to implement than Flash ADCs. Moreover, Pipeline ADCs are less complex than Flash ADCs that offer similar resolution. Also, the power drain of Pipeline ADCs is lesser than that of Flash ADCs. However, Pipeline ADCs introduce a finite latency between the analog sample (of an analog signal) and the digital representation of the sample. The duration of the latency is dependent on the number of stages in the pipeline. Another drawback of Pipeline ADCs is that when the resolution of conversion is increased, the conversion speed of the ADC reduces. This is due to the fact that the input stages have to be more accurate in resolving the input signal, resulting in slower conversion speeds because of the settling time of the amplifier. Time interleaving of multiple Pipeline ADCs has been demonstrated in an effort to address this drawback. However, the time interleaving technique is limited by the accuracy of the sampling interval relative to the other stages, the relative gain and offset match, and the timing jitter of the sampling clocks.
Another class of ADCs is the Successive Approximation ADCs. Successive Approximation ADCs also allow high resolutions. However, Successive Approximation ADCs are slow since they usually require N cycles to perform the analog-to-digital conversion for a resolution of N bits.
A high-speed architecture for analog-to-digital conversion is used in Folding ADCs in which the signal is “folded” by using several folding amplifiers to replicate the input signal. The digital output signal is produced by detecting zero crossings of the folding amplifiers. Though Folding ADCs are faster than Successive Approximation ADCs, the folding technique requires many folding amplifiers for higher resolution. This results in relatively high power consumption. Also, the main disadvantage of the folding ADC is the reduced bandwidth due to the internal multiplication of the input signal frequency with the folding rate. The number of folding amplifiers can be reduced by using interpolation. However interpolation, when used with folding limits the resulting dynamic range of the converter.
Another popular class of ADCs is the Sigma-Delta ADC. The Sigma-Delta ADCs allow much higher resolutions (10 to 24 bits). However, these ADCs are relatively slow since the requisite level resolution is achieved by oversampling the input signal and noise shaping. Thus, the performance of Sigma-Delta ADCs is directly influenced by the oversampling ratio used by the ADC. There are primarily two kinds of Sigma-Delta ADCs used for advanced wideband applications: Multi-bit Sigma-Delta ADCs and Continuous Time Sigma-Delta ADCs. Multi-bit Sigma Delta ADCs do not require a high oversampling ratio, but have very high power dissipation (approaching 40–50 mW for W-CDMA). On the other hand Continuous Time Sigma Delta ADCs have low analog power dissipation (<5 mW), but require high sampling frequencies (300 MHz). This results in increased power dissipation.
Another approach to analog-to-digital conversion has been described in U.S. Pat. No. 5,548,286, titled “Analogue and digital convertors using pulse edge modulators with non-linearity error correction”, assigned to B&W Loudspeakers Ltd. The patent discloses an ADC using pulse edge modulation. The pulse edge modulation technique is also known as pulse width modulation (PWM). An advantage of the disclosed approach is that it provides a means for performing multi-bit quantization within the sigma-delta loop using only a single comparator. A second advantage is that the PWM signal visits only two distinct amplitude levels. This makes the implementation of the feedback DAC in the sigma-delta loop much easier. However, the disclosed approach suffers from the following drawbacks. The sawtooth waveform required in the disclosed approach is difficult to generate at high speeds with linearity and low noise. Both these properties directly affect the performance of the ADC. Thus, the signal-to-noise ratio (SNR) of the output of the ADC is adversely affected for high-speed conversion. This limits the bandwidth of the input signal for which the ADC can function satisfactorily.
Thus, there is a need for an ADC that offers high resolution of conversion and does not require a high oversampling rate. Also, there is a need for an ADC that has low power dissipation and achieves high SNR for high-speed conversions. Further, there is a need for an ADC that does not require complex (or costly) hardware for implementation.